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DATA SHEET
MOS INTEGRATED CIRCUIT
PD4616112-X
16M-BIT CMOS MOBILE SPECIFIED RAM 1M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
Description
The PD4616112-X is a high speed, low power, 16,777,216 bits (1,048,576 words by 16 bits) CMOS mobile specified RAM featuring low power static RAM compatible function and pin configuration. The PD4616112-X is fabricated with advanced CMOS technology using one-transistor memory cell. The PD4616112-X is packed in 48-pin TAPE FBGA.
Features
* 1,048,576 words by 16 bits organization * Fast access time: 85, 95 ns (MAX.) * Byte data control: /LB (I/O0 - I/O7), /UB (I/O8 - I/O15) * Low voltage operation: VCC = 2.6 to 3.1 V * Operating ambient temperature: TA = -25 to +85 C * Output Enable input for easy application * Chip Enable input: /CS pin * Standby Mode input: MODE pin * Standby Mode1: Normal standby (Memory cell data hold valid) * Standby Mode2: Memory cell data hold invalid
Product name
Access time ns (MAX.)
Operating supply Voltage
Operating ambient temperature C
Supply current At operating mA (MAX.) 35 At standby
A (MAX.)
70 / 10
PD4616112-BxxLX
85, 95
2.6 to 3.1
-25 to +85
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. M15794EJ2V0DS00 (2nd edition) Date Published January 2002 NS CP (K) Printed in Japan
The mark 5 shows major revised points.
(c)
2001
PD4616112-X
Ordering Information
Part number Package Access time ns (MAX.) Operating supply voltage V Operating temperature C -25 to +85 B version Remark
PD4616112F9-B85LX-BC2 PD4616112F9-B95LX-BC2
48-pin TAPE FBGA (8 x 6)
85 95
2.6 to 3.1
Marking Image
Part number Marking (XX) L1 L2
PD4616112F9-B85LX-BC2 PD4616112F9-B95LX-BC2
J MS16M0-XX
Index mark
Lot number
2
Data Sheet M15794EJ2V0DS
PD4616112-X
Pin Configuration
/xxx indicates active low signal.
48-pin TAPE FBGA (8 x 6)
Top View Bottom View
A B C D E F G H
1
2
3
4
5
6
6
5
4
3
2
1
1 A B C D E F G H /LB I/O8 I/O9 GND VCC I/O14 I/O15 A18
2 /OE /UB I/O10 I/O11 I/O12 I/O13 A19 A8
3 A0 A3 A5 A17 GND A14 A12 A9
4 A1 A4 A6 A7 A16 A15 A13 A10
5 A2 /CS I/O1 I/O3 I/O4 I/O5 /WE A11
6 MODE I/O0 I/O2 VCC GND I/O6 I/O7 GND A B C D E F G H
6 MODE I/O0 I/O2 VCC GND I/O6 I/O7 GND
5 A2 /CS I/O1 I/O3 I/O4 I/O5 /WE A11
4 A1 A4 A6 A7 A16 A15 A13 A10
3 A0 A3 A5 A17 GND A14 A12 A9
2 /OE /UB I/O10 I/O11 I/O12 I/O13 A19 A8
1 /LB I/O8 I/O9 GND VCC I/O14 I/O15 A18
A0 - A19 I/O0 - I/O15 /CS MODE /WE
: Address inputs : Data inputs / outputs : Chip Select : Standby mode : Write enable
/OE /LB, /UB VCC GND
: Output enable : Byte data select : Power supply : Ground
Remark Refer to Package Drawing for the index mark.
Data Sheet M15794EJ2V0DS
3
PD4616112-X
Block Diagram
Standby mode control
VCC GND Refresh control
Refresh counter A0 A19 Row decoder Address buffer
Memory cell array 16,777,216 bits
I/O0 - I/O7 I/O8 - I/O15 Input data controller
Sense amplifier / Switching circuit
Column decoder
Output data controller
Address buffer
/CS MODE
/LB /UB /WE
/OE
4
Data Sheet M15794EJ2V0DS
PD4616112-X
Truth Table
/CS MODE /OE x x H L /WE x x H H /LB x x x L L H H x L L L H H /UB x x x L H L H L H L H Mode I/O0 - I/O7 H H L H L H Not selected (Standby Mode 1) Not selected (Standby Mode 2) Output disable Word read Lower byte read Upper byte read Output disable Word write Lower byte write Upper byte write Write abort High impedance High impedance High impedance DOUT DOUT High impedance High impedance DIN DIN High impedance High impedance I/O I/O8 - I/O15 High impedance High impedance High impedance DOUT High impedance DOUT High impedance DIN High impedance DIN High impedance ISB1 ISB2 ICCA Supply current
Caution MODE pin must be fixed to High except Standby Mode 2. Remark x: VIH or VIL
Initialization
The PD4616112-X is initialized in the power-on sequence according to the following. (1) To stabilize internal circuits, before turning on the power, a 200 s or longer wait time must precede any signal toggling. (2) After the wait time, read operation must be performed at least 3 times. After that, it can be normal operation.
Initialization Timing Chart
VCC (MIN.) VCC
Address (Input)
MODE (Input)
VIH (MIN.)
tRC /CS (Input) VIH (MIN.)
tCP
Power On Wait Time 200 s
Read Operation 3 times
Normal Operation
Cautions 1. Following power application, make MODE and /CS high level during the wait time interval. 2. Following power application, make MODE high level during the wait time and three read operations. 3. The read operation must satisfy the specs described on page 10 (Read Cycle (B Version)). 4. The address is don't care (VIH or VIL) during read operation. 5. Read operation must be executed with toggled the /CS pin. 6. To prevent bus contention, it is recommended to set /OE to high level. 7. Do not input data to the I/O pins if /OE is low level during a read operation.
Data Sheet M15794EJ2V0DS
5
PD4616112-X
Electrical Specifications
Absolute Maximum Ratings
Parameter Supply voltage Input / Output voltage Operating ambient temperature Storage temperature Symbol VCC VT TA Tstg -0.5
Note
Condition -0.5
Rating
Note
Unit V V C C
to +3.3
to VCC + 0.4 (3.3 V MAX). -25 to +85 -55 to +125
Note -1.0 V (MIN.) (Pulse width: 30 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol Condition
PD4616112-BxxLX
MIN. MAX. 3.1 VCC+0.3 0.2 VCC +85
Unit
Supply voltage High level input voltage Low level input voltage Operating ambient temperature
VCC VIH VIL TA
2.6 0.8 VCC -0.3
Note
V V V C
-25
Note -0.5 V (MIN.) (Pulse width: 30 ns)
Capacitance (TA = 25C, f = 1 MHz)
Parameter Input capacitance Input / Output capacitance Symbol CIN CI/O Test condition VIN = 0 V VI/O = 0 V MIN. TYP. MAX. 8 10 Unit pF pF
Remarks 1. VIN: Input voltage VI/O: Input / Output voltage 2. These parameters are not 100% tested.
6
Data Sheet M15794EJ2V0DS
PD4616112-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter Symbol Test condition MIN. Input leakage current I/O leakage current ILI ILO VIN = 0 V to VCC VI/O = 0 V to VCC, /CS = VIH or /WE = VIL or /OE = VIH Operating supply current Standby supply current ICCA ISB1 ISB2 High level output voltage Low level output voltage VOH VOL /CS = VIL, Minimum cycle time, II/O = 0 mA /CS VCC - 0.2 V, MODE VCC - 0.2 V /CS VCC - 0.2 V, MODE 0.2 V IOH = -0.5 mA IOL = 1 mA 0.8 VCC 0.2 VCC 35 70 10 V V mA -1.0 -1.0
PD4616112-BxxLX
TYP. MAX. +1.0 +1.0
Unit
A A
A
Remarks 1. VIN: Input voltage VI/O: Input / Output voltage 2. These DC characteristics are in common regardless of product classifications.
Data Sheet M15794EJ2V0DS
7
PD4616112-X
Standby Mode State Machine
Power on
/CS = VIH, MODE = VIH
Wait 200 s Dummy read operation (3 times)
Initial State
/CS = VIL /CS = VIH, MODE = VIH
Active
MODE = VIH
/CS = VIH, MODE = VIH
/CS = VIH, MODE = VIL
/CS = VIL, MODE = VIH
Standby Mode1
/CS = VIH, MODE = VIL
Standby Mode2
Standby Mode Characteristics
Standby Mode Mode 1 Mode 2 Memory Cell Data Hold Valid Invalid Standby Supply Current (A) 70 (ISB1) 10 (ISB2)
8
Data Sheet M15794EJ2V0DS
PD4616112-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions [ PD4616112-B85LX, PD4616112-B95LX ] Input Waveform (Rise and Fall Time 5 ns)
Vcc 0.8 Vcc Vcc/2 0.2 Vcc GND 5ns Test points Vcc/2
Output Waveform
Vcc/2
Test points
Vcc/2
Output Load AC characteristics directed with the note should be measured with the output load shown in Figure 1.
Figure 1
CL: 50 pF 5 pF (tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW)
ZO = 50 I/O (Output)
50
CL
VCC/2
Data Sheet M15794EJ2V0DS
9
PD4616112-X
Read Cycle (B version)
Parameter Symbol
PD4616112-B85LX
MIN. MAX. 10,000 10,000 10 10 85 85 35 35 10 10 5 5 25 25 25
PD4616112-B95LX
MIN. 95 95 MAX. 10,000 10,000 20 10 95 95 40 40 10 10 5 5 25 25 25
Unit
Note
Read cycle time Identical address read cycle time Address skew time /CS pulse width Address access time /CS access time /OE to output valid /LB, /UB to output valid Output hold from address change /CS to output in low impedance /OE to output in low impedance /LB, /UB to output in low impedance /CS to output in high impedance /OE to output in high impedance /LB, /UB to output in high impedance
tRC tRC1 tSKEW tCP tAA tACS tOE tBA tOH tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ
85 85
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1 2 3
4
5
Notes 1. One read cycle (tRC) must satisfy the minimum value (tRC(MIN.)) and maximum value (tRC(MAX.) = 10 s). tRC indicates the time from the /CS low level input point or address change start point, whichever is later, to the /CS high level input point or the next address change start point, whichever is earlier. As a result, there are the following four conditions for tRC. 1) Time from address change start point to /CS high level input point 2) Time from address change start point to next address change start point 3) Time from /CS low level input point to next address change start point 4) Time from /CS low level input point to /CS high level input point (address access) (address access) (/CS access) (/CS access)
2. The identical address read cycle time (tRC1) is the cycle time of one read operation when performing continuous read operations toggling /OE , /LB, and /UB with the address fixed and /CS low level. Perform settings so that the sum (tRC) of the identical address read cycle times (tRC1) is 10 s or less. 3. tSKEW indicates the following three types of time depending on the condition. 1) When switching /CS from high level to low level, tSKEW is the time from the /CS low level input point until the next address is determined. 2) When switching /CS from low level to high level, tSKEW is the time from the address change start point to the /CS high level input point. 3) When /CS is fixed to low level, tSKEW is the time from the address change start point until the next address is determined. Since specs are defined for tSKEW only when /CS is active, tSKEW is not subject to limitations when /CS is switched from high level to low level following address determination, or when the address is changed after /CS is switched from low level to high level. 4. Regarding tAA and tACS, only tAA is satisfied during address access (refer to 1) and 2) of Note 1), and only tACS is satisfied during /CS access (refer to 3) of Note 1). 5. Regarding tBA and tOE, only tBA is satisfied if /OE becomes active later than /UB and /LB, and only tOE is satisfied if /UB and /LB become active before /OE. 10
Data Sheet M15794EJ2V0DS
PD4616112-X
Read Cycle Timing Chart 1
tSKEW tSKEW
Address (Input)
tCP tRC tCP
/CS (Input) tACS tCLZ /OE (Input) tOE tOLZ /LB, /UB (Input) tBA tBLZ High impedance I/O (Output) tBHZ tOH tOHZ tCHZ
Data out
tRC tSKEW tSKEW
Address (Input)
tCP tCP
tACS
/CS (Input) tCLZ tCHZ
/OE (Input) tOE tOLZ /LB, /UB (Input) tBA tBLZ High impedance I/O (Output) tBHZ tOHZ
Data out
Caution If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (tRC), none of the data can be guaranteed.
Remark In read cycle, /WE should be fixed to High.
Data Sheet M15794EJ2V0DS
11
12
Read Cycle Timing Chart 2
tRC tSKEW tSKEW
tRC tSKEW tSKEW
Address (Input)
tCP tACS
Data Sheet M15794EJ2V0DS
tRC tAA
tRC
tCP
tRC
tAA
/CS (Input) tCLZ tCHZ tACS tCLZ tOE tOLZ /LB, /UB (Input) tBA tBLZ High impedance I/O (Output) tOH tOH tBLZ tBHZ tBA tOH tBLZ tBHZ tBA tBHZ tOHZ tCHZ tACS tCLZ tCHZ
/OE (Input)
Data out
Data out
Data out
Data out
Data out
PD4616112-X
Caution If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (tRC), none of the data can be guaranteed.
Remark In read cycle, /WE should be fixed to High.
Read Cycle Timing Chart 3
tRC tSKEW tSKEW tRC tSKEW tRC tSKEW tRC tSKEW tRC
Address (Input)
tACS /CS (Input) tCLZ
tAA
tAA
Data Sheet M15794EJ2V0DS
/OE (Input) tOLZ /LB (Input)
tOE tOHZ tOLZ tBA tBHZ tBLZ tOH tBLZ
tOE tOHZ tOLZ tBA tBHZ tOH
tOE tOHZ
I/O0~7 (Output)
Hi-Z
Data out
Data out
/UB (Input)
tBA
tBHZ tOH tBLZ
tBA tBHZ tOH
tBLZ I/O8~15 (Output) High impedance
Data out
Data out
PD4616112-X
Caution If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (tRC), none of the data can be guaranteed.
13
Remark In read cycle, /WE should be fixed to High.
PD4616112-X
Read Cycle Timing Chart 4
tRC tSKEW tSKEW
Address (Input)
tRC1 tACS /CS (Input) tOE /OE (Input) tOLZ tOHZ tOE tOLZ tOHZ
Note
tRC1
Note
tBA tBLZ /LB, /UB (Input)
tBA tBLZ
tBHZ
tBHZ
I/O (Output) High impedance
Data out
Data out
High impedance
Caution If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (tRC), none of the data can be guaranteed.
Note To perform a continuous read toggling /OE, /UB, and /LB with /CS low level at an identical address, make settings so that the sum (tRC) of the identical address read cycle times (tRC1) is 10 s or less.
Remark In read cycle, /WE should be fixed to High.
14
Data Sheet M15794EJ2V0DS
PD4616112-X
Write Cycle (B version)
Parameter Symbol
PD4616112-B85LX
MIN. MAX. 10,000 10,000 10 40 30 35 30 20 10 0 20 20 0 5 25 25 5
PD4616112-B95LX
MIN. 95 95 MAX. 10,000 10,000 20 50 35 45 35 20 10 0 20 25 0 5 25 25 5
Unit
Note
Write cycle time Identical address write cycle time Address skew time /CS to end of write /LB, /UB to end of write Address valid to end of write Write pulse width Write recovery time /CS pulse width Address setup time Byte write hold time Data valid to end of write Data hold time /OE to output in low impedance /WE to output in high impedance /OE to output in high impedance Output active from end of write
tWC tWC1 tSKEW tCW tBW tAW tWP tWR tCP tAS tBWH tDW tDH tOLZ tWHZ tOHZ tOW
85 85
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1 2 3 4
5
Notes 1. One write cycle (tWC) must satisfy the minimum value (tWC(MIN.)) and the maximum value (tWC(MAX.) = 10 s). tWC indicates the time from the /CS low level input point or address change start point, whichever is after, to the /CS high level input point or the next address change start point, whichever is earlier. As a result, there are the following four conditions for tWC. 1) Time from address change start point to /CS high level input point 2) Time from address change start point to next address change start point 3) Time from /CS low level input point to next address change start point 4) Time from /CS low level input point to /CS high level input point 2. The identical address read cycle time (tWC1) is the cycle time of one write cycle when performing continuous write operations with the address fixed and /CS low level, changing /LB and /UB at the same time, and toggling /WE, as well as when performing a continuous write toggling /LB and /UB. Make settings so that the sum (tWC) of the identical address write cycle times (tWC1) is 10 s or less. 3. tSKEW indicates the following three types of time depending on the condition. 1) When switching /CS from high level to low level, tSKEW is the time from the /CS low level input point until the next address is determined. 2) When switching /CS from low level to high level, tSKEW is the time from the address change start point to the /CS high level input point. 3) When /CS is fixed to low level, tSKEW is the time from the address change start point until the next address is determined. Since specs are defined for tSKEW only when /CS is active, tSKEW is not subject to limitations when /CS is switched from high level to low level following address determination, or when the address is changed after /CS is switched from low level to high level.
Data Sheet M15794EJ2V0DS
15
PD4616112-X
4. Definition of write start and write end
/CS Write start pattern 1 Write start pattern 2 Write start pattern 3 Write end pattern 1 Write end pattern 2 H to L L L L L /WE L H to L L L to H L /LB, /UB L L H to L L L to H Status If /WE, /LB, /UB are low level, time when /CS changes from high level to low level If /CS, /LB, /UB are low level, time when /WE changes from high level to low level If /CS, /WE are low level, time when /LB or /UB changes from high level to low level If /CS, /WE, /LB, /UB are low level, time when /WE changes from low level to high level When /CS, /WE, /LB, /UB are low level, time when /LB or /UB changes from low level to high level
5. Definition of write end recovery time (tWR) 1) Time from write end to address change start point, or from write end to /CS high level input point 2) When /CS, /LB, /UB are low level and continuously written to the identical address, time from /WE high level input point to /WE low level input point 3) When /CS, /WE are low level and continuously written to the identical address, time from /LB or /UB high level input point, whichever is later, to /LB or /UB low level input point, whichever is earlier. 4) When /CS is low level and continuously written to the identical address, time from write end to point at which /WE , /LB, or /UB starts to change from high level to low level, whichever is earliest.
16
Data Sheet M15794EJ2V0DS
PD4616112-X
Write Cycle Timing Chart 1
tWC tSKEW tSKEW tWC
Address (Input)
tCW /CS (Input)
tCP
tCW
tWP /WE (Input) tAS /LB, /UB (Input) tBW
tWR
tAS
tWP
tWR
tBW
tDW I/O (Input) High impedance
tDH High impedance
tDW
tDH
Data in
Data in
tSKEW
tWC
tSKEW
tWC
tSKEW
Address (Input)
tCW /CS (Input)
tCP
tCW
tWP /WE (Input) tBW /LB, /UB (Input)
tWR
tWP
tWR
tBW
tDW I/O (Input) High impedance
tDH High impedance
tDW
tDH
Data in
Data in
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (tWC), none of the data can be guaranteed.
Remark
Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB.
Data Sheet M15794EJ2V0DS
17
PD4616112-X
Write Cycle Timing Chart 2 (/WE Controlled)
tWC tSKEW tSKEW tWC tSKEW tWC tSKEW tSKEW
Address (Input)
tCW /CS (Input) tAS /WE (Input) tWP tAS tAW tWR tOW
tAW
tAW
tCP
tAS
tWP tWHZ
tWR
tWP
tWR
/OE (Input) tDW I/O (Input / Output) High impedance tDH tOLZ tOHZ Indefinite data out
High impedance
tDW
tDH
tDW
tDH
Data in
Data in
High impedance
High impedance
Data in
High impedance
tWC tSKEW tSKEW
Address (Input)
Note Note
tWC1 /CS (Input) tAS /WE (Input) tBW /LB, /UB (Input) tWP
tWC1
tWR
tWP
tWR
tDW I/O (Input) High impedance
tDH
tDW
tDH
Data in High impedance
Data in High impedance
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (tWC), none of the data can be guaranteed.
Note If /LB and /UB are changed at the same time with /CS low level and a continuous write operation toggling /WE is performed, make settings so that the sum (tWC) of the identical address write cycle time (tWC1) is 10 s or less.
Remarks 1. Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB. 2. When /WE is at Low, the I/O pins are always high impedance. When /WE is at High, read operation is executed. Therefore /OE should be at High to make the I/O pins high impedance. 18
Data Sheet M15794EJ2V0DS
PD4616112-X
Write Cycle Timing Chart 3 (/CS Controlled)
Address (Input)
tWC /CS (Input) tAS tCW tWR tAS
tWC
tCW
tWR
/WE (Input)
/LB, /UB (Input) tDW I/O (Input) tDH tDW tDH
High impedance
Data in
High impedance
Data in
High impedance
Address (Input)
tWC /CS (Input) tAS tCW tWR tAS
tWC
tCW
tWR
/WE (Input)
/LB, /UB (Input) tDW I/O (Input) tDH tDW tDH
Data in High impedance High impedance
Data in High impedance
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (tWC), none of the data can be guaranteed.
Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB.
Data Sheet M15794EJ2V0DS
19
PD4616112-X
Write Cycle Timing Chart 4 (/LB, /UB Controlled 1)
tWC tSKEW Address (Input) tSKEW tWC
tCW /CS (Input)
tAW
tWP /WE (Input) tAS /LB, /UB (Input) tBW tWR tAS tBW tWR
tDW I/O (Input) High impedance Data in
tDH High impedance
tDW Data in
tDH
tWC tWC Address (Input) tSKEW tSKEW
tCW /CS (Input)
tAW
tWP /WE (Input) tAS /LB, /UB (Input) tBW tWR tAS tBW tWR
tDW I/O (Input) High impedance Data in
tDH High impedance
tDW Data in
tDH
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (tWC), none of the data can be guaranteed.
Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB.
20
Data Sheet M15794EJ2V0DS
PD4616112-X
Write Cycle Timing Chart 5 (/LB, /UB Controlled 2)
tWC tSKEW tSKEW
Address (Input)
tWC1 Note /CS (Input)
tWC1
Note
tWP /WE (Input) tAS /LB, /UB (Input) tBW tWR tBW tWR
tDW I/O (Input) High impedance
tDH
tDW
tDH
Data in
High impedance
Data in
High impedance
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (tWC), none of the data can be guaranteed.
Note If /LB and /UB are changed at the same time with /CS low level and a continuous write operation toggling /WE is performed, make settings so that the sum (tWC) of the identical address write cycle time (tWC1) is 10 s or less.
Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB.
Data Sheet M15794EJ2V0DS
21
PD4616112-X
Write Cycle Timing Chart 6 (/LB, /UB Independent Controlled 1)
tWC Address (Input)
tWC1 Note /CS (Input) tCW tWP /WE (Input)
tWC1 Note
/LB (Input) tAS tBW /UB (Input) tDW Data in High impedance tDW I/O8 - 15 (Input) High impedance tDH tDH tWR tBW tWR
I/O0 - 7 (Input)
Data in High impedance High impedance
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (tWC), none of the data can be guaranteed.
Note If /LB and /UB are changed at the same time with /CS low level and a continuous write operation toggling /WE is performed, make settings so that the sum (tWC) of the identical address write cycle time (tWC1) is 10 s or less.
Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB.
22
Data Sheet M15794EJ2V0DS
PD4616112-X
Write Cycle Timing Chart 7 (/LB, /UB Independent Controlled 2)
Address (Input)
tWC /CS (Input) tCW tCW tWP tWP /WE (Input) tBW /LB (Input) tAS tBWH tBW /UB (Input) tAS tDW Data in High impedance tDW I/O8 - 15 (Input) High impedance tDH tDH tWR tWR
I/O0 - 7 (Input)
Data in High impedance High impedance
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (tWC), none of the data can be guaranteed.
Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB.
Data Sheet M15794EJ2V0DS
23
PD4616112-X
Read Write Cycle (B version)
Parameter Read write cycle time Byte write setup time Byte read setup time Symbol tRWC tBWS tBRS 20 20 MIN. MAX. 10,000 Unit ns ns ns Note 1, 2
Notes 1. Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1) is 10 s or less when a write is performed at the identical address using /UB following a read using /LB with /CS low level, or when a write is performed using /LB following a read using /UB. 2. Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1) is 10 s or less when a read is performed at the identical address using /UB following a write using /LB with /CS low level, or when a read is performed using /LB following a write using /UB.
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Data Sheet M15794EJ2V0DS
PD4616112-X
Read Write Cycle Timing Chart 1 (/LB, /UB Independent Controlled 1)
tRWC Address (Input) tRC1 Note tAA /CS (Input) tACS tWP /WE (Input) tBWS tWC1 Note
/LB (Input) tBW /UB (Input) tWR
tCLZ tBLZ tBHZ Data out High impedance tDW High impedance tDH
I/O0 - 7 (Output)
I/O8 - 15 (Input)
Data in High impedance High impedance
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1), none of the data can be guaranteed.
Note Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1) is 10 s or less when a write is performed at the identical address using /UB following a read using /LB with /CS low level, or when a write is performed using /LB following a read using /UB.
Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB.
Data Sheet M15794EJ2V0DS
25
PD4616112-X
Read Write Cycle Timing Chart 2 (/LB, /UB Independent Controlled 2)
tRWC Address (Input) tWC1 Note tCW /CS (Input) tWR tWP /WE (Input) tRC1
Note
tBW /LB (Input) tAS tBRS /UB (Input) tDW Data in High impedance tBLZ tBA High impedance tBHZ tDH
I/O0 - 7 (Input)
I/O8 - 15 (Output)
Data out High impedance
High impedance
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1), none of the data can be guaranteed.
Note Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1) is 10 s or less when a write is performed at the identical address using /UB following a read using /LB with /CS low level, or when a write is performed using /LB following a read using /UB.
Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB.
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Data Sheet M15794EJ2V0DS
PD4616112-X
Read Write Cycle Timing Chart 3 (/LB, /UB Independent Controlled 3)
tRWC Address (Input) tWC1Note tCW /CS (Input) tWP /WE (Input) tAS tBW /LB (Input) tWR tRC1
Note
/UB (Input) tDW Data in High impedance tBLZ tBA High impedance tBHZ tDH
I/O0 - 7 (Input)
I/O8 - 15 (Output)
Data out High impedance
High impedance
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1), none of the data can be guaranteed.
Note Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address write cycle time (tWC1) is 10 s or less when a write is performed at the identical address using /UB following a read using /LB with /CS low level, or when a write is performed using /LB following a read using /UB.
Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB.
Data Sheet M15794EJ2V0DS
27
PD4616112-X
Standby Mode 2 entry and recovery Timing Chart
Address (Input)
MODE (Input) tRC /CS (Input) tCM tCP
Standby Mode 2 (Data invalid)
Wait Time 200 s
Read Operation 3 times
Normal Operation
Parameter /CS High to MODE Low
Symbol tCM
MIN. 0
MAX.
Unit ns
Note
Cautions 1. Make MODE and /CS high level during the wait time. 2. Make MODE high level during the wait time and three read operations. 3. The read operation must satisfy the specs described on page 10 (Read Cycle (B Version)). 4. The read operation address can be either VIH or VIL. 5. Perform reading by toggling /CS. 6. To prevent bus contention, it is recommended to set /OE to high level. 7. Do not input data to the I/O pins if /OE is low level during a read operation.
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Data Sheet M15794EJ2V0DS
PD4616112-X
Package Drawing
48-PIN TAPE FBGA (8x6)
ZE E w SB ZD B
A D
6 5 4 3 2 1 HGFEDCBA
INDEX MARK
w
SA
INDEX MARK
A y1 S A2 S
y
S
e
A1
M
b
x
S AB
ITEM D E w e A A1 A2 b x y y1 ZD ZE MILLIMETERS 6.00.1 8.00.1 0.2 0.75 0.940.10 0.240.05 0.70 0.400.05 0.08 0.1 0.2 1.125 1.375 P48F9-75-BC2
Data Sheet M15794EJ2V0DS
29
PD4616112-X
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the PD4616112-X.
Type of Surface Mount Device
PD4616112F9-BxxLX-BC2: 48-pin TAPE FBGA (8 x 6)
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Data Sheet M15794EJ2V0DS
PD4616112-X
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet M15794EJ2V0DS
31
PD4616112-X
* The information in this document is current as of January, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00. 4

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